Sunday, 23 January 2011
The Synopsys DesignWare team in Dublin is responsible for the design, verification, validation and productization of many complex IP blocks for the Synopsys DesignWare Library and DesignWare Cores such as PCIe Express, DDR 2/3 memory and protocol controllers.
The successful candidates will contribute to the development of these complex IP blocks, working at all levels, concept, architectural definition, block specification, design, implementation and verification.
- Successful track record in project work.
- Design or verification experience.
- Exposure to Verilog/VHDL/System Verilog
- Knowledge of IC Design flows.
- Unix, Perl and Tcl Scripting Knowledge.
- Good problem solving/communication skills.
- Some short term travel to US